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Mario D Nemirovsky

from San Francisco, CA
Age ~65

Mario Nemirovsky Phones & Addresses

  • San Francisco, CA
  • San Jose, CA
  • Los Gatos, CA
  • 19750 Northampton Dr, Saratoga, CA 95070 (408) 252-7800 (408) 996-7762
  • Goleta, CA
  • Cupertino, CA
  • Kokomo, IN

Public records

Vehicle Records

Mario Nemirovsky

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Address:
200 Winchester Cir APT D214, Los Gatos, CA 95032
Phone:
(408) 996-7762
VIN:
WBXPC93427WF03163
Make:
BMW
Model:
X3
Year:
2007

Resumes

Resumes

Mario Nemirovsky Photo 1

Mario Nemirovsky

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Location:
San Francisco Bay Area
Industry:
Computer & Network Security
Mario Nemirovsky Photo 2

Vp Chief Scientist At Conseco

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Position:
vp chief scientist at Conseco
Location:
San Francisco Bay Area
Industry:
Computer Networking
Work:
Conseco
vp chief scientist

Publications

Us Patents

Interstream Control And Communications For Multi-Streaming Digital Processors

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US Patent:
6389449, May 14, 2002
Filed:
Mar 22, 1999
Appl. No.:
09/273810
Inventors:
Mario D. Nemirovsky - Saratoga CA
Adolfo M. Nemirovsky - San Jose CA
Narendra Sankar - Santa Clara CA
Assignee:
Clearwater Networks, Inc. - Los Gatos CA
International Classification:
G06F 900
US Classification:
709108, 712228
Abstract:
A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams; and interstream control mechanisms whereby any stream may effect the operation of any other stream. In various embodiments the interstream control mechanisms include mechanisms for accomplishing one or more of enabling or disabling another stream, putting another stream into a sleep mode or awakening another stream from a sleep mode, setting priorities for another stream relative to access to functional resources, and granting blocking access by another stream to functional resources. A Master Mode is taught, wherein one stream is granted master status, and thereby may exert any and all available control mechanisms relative to other streams without interference by any stream. Supervisory modes are taught as well, wherein control may be granted from minimal to full control, with compliance of controlled streams, which may alter or withdraw control privileges. Various mechanisms are disclosed, including a mechanism wherein master status and interstream control hierarchy is recorded and amended by at least one on-chip bit map.

Method And Apparatus For Improved Computer Load And Store Operations

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US Patent:
20090187739, Jul 23, 2009
Filed:
Mar 26, 2009
Appl. No.:
12/411913
Inventors:
Mario NEMIROVSKY - Los Gatos CA,
Enrique Musoll - San Jose CA,
Narendra Sankar - Campbell CA,
Stephen Melvin - Los Gatos CA,
International Classification:
G06F 9/315
US Classification:
712204, 712E09034
Abstract:
Load and store operations in computer systems are extended to provide for Stream Load and Store and Masked Load and Store. In Stream operations, a CPU executes a Stream instruction that indicates, by appropriate arguments, a first address in memory or a first register in a register file from whence to begin reading data entities, and a first address or register from whence to begin storing the entities, and a number of entities to be read and written. In Masked Load and Masked Store operations stored masks are used to indicate patterns relative to first addresses and registers for loading and storing. Bit-string vector methods are taught for masks.

In-Circuit Emulator For Emulating Native Clustruction Execution Of A Microprocessor

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US Patent:
58570942, Jan 5, 1999
Filed:
Mar 28, 1997
Appl. No.:
8/827581
Inventors:
Mario D. Nemirovsky - San Jose CA
Assignee:
National Semiconductor Corp. - Santa Clara CA
International Classification:
G06F 9455
US Classification:
395500
Abstract:
An integrated circuit (IC) includes multiple circuits and functions which share multiple internal signal buses, three physical and five logical, according to distributed bus access and control arbitration. The multiple internal signal buses are shared among three tiers of internal circuit functions: a central processing unit and a DMA controller; a DRAM controller and a bus interface unit; and peripheral interface circuits, such as PCMCIA and display controllers. Two of the physical buses correspond to two of the logical buses and are used for communications within the IC. The third physical bus corresponds to three of the logical buses and is used for communications between the IC and circuits external to the IC. Arbitration for accessing and controlling the various signal buses is distributed both within and among the three tiers of internal circuit functions. Maximum performance is thereby achieved from the circuit functions accessed most frequently, while still achieving high performance from those circuit functions accessed less frequently.

Programmable Vehicle Anti-Theft System

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US Patent:
49909061, Feb 5, 1991
Filed:
Nov 29, 1988
Appl. No.:
7/277276
Inventors:
Curtis N. Kell - Flora IN
R. Clark Griffin - Dayton OH
John M. Dikeman - Kokomo IN
Mario D. Nemirovsky - Goleta CA
Assignee:
Delco Electronics Corporation - Kokoma IN
International Classification:
H04B 100
US Classification:
340825310
Abstract:
A vehicle anti-theft device is disclosed which includes an electronically erasable programmable read only memory (EEPROM) which stores a modifiable code which must be matched by an input code in order to start the vehicle. The ignition key includes a resistor pellet, engaged by contact in the ignition lock assembly, which is measured to provide the input code. To avoid problems associated with intermittent contact engagement with the resistor pellet, circuitry is provided to control the resistor measurement cycle.

Systems And Methods For Creating, Managing And Communicating Users And Applications On Spontaneous Area Networks

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US Patent:
20130301405, Nov 14, 2013
Filed:
Jul 22, 2013
Appl. No.:
13/947190
Inventors:
JORGE GARCIA VIDAL - BARCELONA,
DANIEL NEMIROVSKY - SAN FRANCISCO CA,
MARIO NEMIROVSKY - SAN FRANCISCO CA,
Assignee:
MIRAVEO, INC. - San Jose CA
International Classification:
H04W 84/18
US Classification:
370229, 370338
Abstract:
A Spontaneous Area Network (SPAN) is formed by mobile and fixed nodes using wireless transmission links between nodes, usually in a nearby geographical area. Applications allow users to create, join, leave, and manage SPANs and groups in a SPAN. Automatic procedures allow nodes to join other SPANs. Transmission power of the wireless network interface is dynamic, varying depending on battery level, type of information to transmit, state and topology of the network. A delay tolerant object layer abstraction creates, modifies, deletes, publishes, and handles Delay Tolerant Distributed Objects (DTDOs). A Patient Transport Protocol (PTP) ensures a reliable transport of information through the network while avoiding congestion conditions. An aggressive and explosive network protocol (AGENET) has routing and forwarding capacities and uses datagrams to establish communication between different nodes of the SPAN. Cooperation and diversity are exploited to react to node mobility that causes frequent changes in network topology and disconnections.

Systems And Methods For Creating, Managing And Communicating Users And Applications On Spontaneous Area Networks

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US Patent:
20130286892, Oct 31, 2013
Filed:
Jun 28, 2013
Appl. No.:
13/930806
Inventors:
JORGE GARCIA VIDAL - BARCELONA,
DANIEL NEMIROVSKY - SAN FRANCISCO CA,
MARIO NEMIROVSKY - SAN FRANCISCO CA,
International Classification:
H04L 12/56
US Classification:
370254
Abstract:
A Spontaneous Area Network (SPAN) is formed by mobile and fixed nodes using wireless transmission links between nodes, usually in a nearby geographical area. Applications allow users to create, join, leave, and manage SPANs and groups in a SPAN. Automatic procedures allow nodes to join other SPANs. Transmission power of the wireless network interface is dynamic, varying depending on battery level, type of information to transmit, state and topology of the network. A delay tolerant object layer abstraction creates, modifies, deletes, publishes, and handles Delay Tolerant Distributed Objects (DTDOs). A Patient Transport Protocol (PTP) ensures a reliable transport of information through the network while avoiding congestion conditions. An aggressive and explosive network protocol (AGENET) has routing and forwarding capacities and uses datagrams to establish communication between different nodes of the SPAN. Cooperation and diversity are exploited to react to node mobility that causes frequent changes in network topology and disconnections.

Mechanism For Managing Resource Locking In A Multi-Threaded Environment

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US Patent:
20100205608, Aug 12, 2010
Filed:
Feb 2, 2010
Appl. No.:
12/698860
Inventors:
Mario D. Nemirovsky - Saratoga CA,
Jeffrey T. Huynh - Milpitas CA,
International Classification:
G06F 9/46
US Classification:
718104
Abstract:
A mechanism is disclosed for implementing resource locking in a massively multi-threaded environment. The mechanism receives from a stream a request to obtain a lock on a resource. In response, the mechanism determines whether the resource is currently locked. If so, the mechanism adds the stream to a wait list. At some point, based upon the wait list, the mechanism determines that it is the stream's turn to lock the resource; thus, the mechanism grants the stream a lock. In this manner, the mechanism enables the stream to reserve and to obtain a lock on the resource. By implementing locking in this way, a stream is able to submit only one lock request. When it is its turn to obtain a lock, the stream is granted that lock. This lock reservation methodology makes it possible to implement resource locking efficiently in a massively multi-threaded environment.

Mechanism For Achieving Packet Flow Control In A Multi-Threaded, Multi-Packet Environment

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US Patent:
20100202292, Aug 12, 2010
Filed:
Jan 29, 2010
Appl. No.:
12/697099
Inventors:
Mario D. Nemirovsky - San Jose CA,
Enrique Musoll - San Jose CA,
Jeffrey T. Huynh - Milpitas CA,
Stephen W. Melvin - San Francisco CA,
International Classification:
H04L 12/56
US Classification:
370235
Abstract:
A processing engine to accomplish a multiplicity of tasks has a multiplicity of processing tribes, each tribe comprising a multiplicity of context register sets and a multiplicity of processing resources for concurrent processing of a multiplicity of threads to accomplish the tasks, a memory structure having a multiplicity of memory blocks, each block storing data for processing threads, and an interconnect structure and control system enabling tribe-to-tribe migration of contexts to move threads from tribe-to-tribe. The processing engine is characterized in that individual ones of the tribes have preferential access to individual ones of the multiplicity of memory blocks.
Mario D Nemirovsky from San Francisco, CA, age ~65 Get Report