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Hormoz Yaghutiel Phones & Addresses

  • 834 Brevins Loop, San Jose, CA 95125
  • 100 Cuttermill Rd, Great Neck, NY 11021
  • New York, NY
  • Englewood, NJ
  • Springfield, NJ
  • Santa Clara, CA
  • Scotch Plains, NJ

Work

Company: Cadence design systems Apr 2003 Address: San Jose, CA Position: Engineering group director

Education

Degree: MBA School / High School: Columbia University - Columbia Business School 1995 to 1997

Skills

Eda • Asic • Soc • Static Timing Analysis • Logic Synthesis • Ic • Vlsi • Semiconductors • Tcl • Physical Design • Verilog • Analog • Formal Verification • Cadence • Algorithms • Debugging • Signal Integrity • Rtl Coding • Fpga • Low Power Design • Perl • Leadership • Integrated Circuit Design • Vhdl • Simulations • Rtl Design • Timing Closure • Cmos • Mixed Signal • Systemverilog • Processors • Functional Verification • Computer Architecture • Timing • Microelectronics • Microprocessors • Hardware Architecture • Circuit Design • Drc • Clock Tree Synthesis • Cadence Virtuoso • Dft • Logic Design • Systemc • Modelsim • Specman • Floorplanning • Lvs • Physical Verification • Primetime

Industries

Computer Software

Resumes

Resumes

Hormoz Yaghutiel Photo 1

Director Of Engineering

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Location:
San Jose, CA
Industry:
Computer Software
Work:
Cadence Design Systems - San Jose, CA since Apr 2003
Engineering Group Director

Get2Chip Nov 1999 - Apr 2003
Vice President of Engineering

Sapphire Design Automation May 1998 - Nov 1999
Director of Engineering

Bell Laboratories - Murray Hill, NJ Aug 1988 - May 1998
Member of Technical Staff
Education:
Columbia University - Columbia Business School 1995 - 1997
MBA
University of California, Berkeley 1983 - 1988
Ph.D., Electrical Engineering and Computer Science
University of Michigan 1978 - 1982
B.S./M.S., Electrical and Computer Engineering
Alborz High School
Skills:
Eda
Asic
Soc
Static Timing Analysis
Logic Synthesis
Ic
Vlsi
Semiconductors
Tcl
Physical Design
Verilog
Analog
Formal Verification
Cadence
Algorithms
Debugging
Signal Integrity
Rtl Coding
Fpga
Low Power Design
Perl
Leadership
Integrated Circuit Design
Vhdl
Simulations
Rtl Design
Timing Closure
Cmos
Mixed Signal
Systemverilog
Processors
Functional Verification
Computer Architecture
Timing
Microelectronics
Microprocessors
Hardware Architecture
Circuit Design
Drc
Clock Tree Synthesis
Cadence Virtuoso
Dft
Logic Design
Systemc
Modelsim
Specman
Floorplanning
Lvs
Physical Verification
Primetime
Hormoz Yaghutiel from San Jose, CA, age ~62 Get Report