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Asif Shakeel Phones & Addresses

  • San Jose, CA
  • 7015 Charmant Dr, San Diego, CA 92122 (858) 638-1957
  • 7545 Charmant Dr, San Diego, CA 92122 (858) 623-9923
  • 7608 Palmilla Dr, San Diego, CA 92122 (858) 638-1957
  • 7665 Palmilla Dr, San Diego, CA 92122 (858) 455-1656
  • 6306 Rancho Mission Rd, San Diego, CA 92108
  • Arlington, MA
  • Haverford, PA
  • La Jolla, CA
  • Worcester, MA
  • Cambridge, MA

Work

Company: Harvard university Jun 2013 Position: Visiting scholar, quantum information group

Education

School / High School: University of California at San Diego- La Jolla, CA Jun 2011 Specialities: Ph. D. in Mathematics

Skills

Public Speaking • Teaching

Industries

Research

Resumes

Resumes

Asif Shakeel Photo 1

Asif Shakeel Arlington, MA

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Work:
Harvard University

Jun 2013 to 2000
Visiting Scholar, Quantum Information Group

Haverford College
Haverford, PA
Jun 2011 to May 2013
Postoctoral Fellow, Department of Physics

Education:
University of California at San Diego
La Jolla, CA
Jun 2011
Ph. D. in Mathematics

Massachusetts Institute of Technology
Cambridge, MA
Aug 1995
Engineering

Asif Shakeel Photo 2

Asif Shakeel

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Location:
Cambridge, Massachusetts
Industry:
Research
Skills:
Public Speaking
Teaching

Publications

Us Patents

System For Adjusting Clock Frequency Based Upon Amount Of Unread Data Stored In Sequential Memory When Reading A New Line Of Data Within A Field Of Data

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US Patent:
6581164, Jun 17, 2003
Filed:
Jan 3, 2000
Appl. No.:
09/476849
Inventors:
Asif Shakeel - San Diego CA
Havard Lee Scott - San Diego CA
Assignee:
Conexant Systems, Inc. - Newport Beach CA
International Classification:
G06F 112
US Classification:
713400, 710 52, 710 57, 710 61, 710310, 713503, 713600
Abstract:
A method for adjusting timing of a secondary system with respect to a reference system is disclosed. The secondary and reference systems include a secondary synchronization signal and a reference synchronization signal, which are used to detect a phase difference between the secondary synchronization signal and the reference synchronization signal. A filtered phase error is generated from the detected phase difference. In addition, a frequency difference is detected between the secondary synchronization signal and the reference synchronization signal, and an instantaneous frequency difference and a filtered frequency error are generated from the detected frequency difference. The filtered phase error and the filtered frequency error are accumulated, and the timing of the secondary system is controlled in accordance with the accumulated filtered phase error, the accumulated filtered frequency error, and the instantaneous frequency difference.

System And Method For Processing Hdtv Format Video Signals

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US Patent:
20020105592, Aug 8, 2002
Filed:
Feb 5, 2001
Appl. No.:
09/777253
Inventors:
Benjamin Felts - Cardiff CA,
Asif Shakeel - San Diego CA,
Dennis Poltz - San Diego CA,
Semion Talpalatsky - San Diego CA,
Assignee:
Conexant Systems, Inc.
International Classification:
H04N003/27
H04N007/16
US Classification:
348/554000, 348/521000
Abstract:
System and method for processing HDTV format video signals have been disclosed. A disclosed embodiment comprises a HDTV timing generator having as inputs a vertical sync and a horizontal sync. The HDTV timing generator outputs a digital HD level signal. The disclosed embodiment further comprises a DAC interface. The DAC interface can include an encoder channel, or more than one encoder channel. The encoder channel can receive a digital HD level signal, a SCART level signal, an NTSC level signal, a PAL level signal, and a SECAM level signal. The encoder channel can further receive a HDTV format data input, a SCART format data input, an NTSC format data input, a PAL format data input, and a SECAM format data input. The output of the DAC interface can be coupled to a DAC which in turn generates an output suitable for display on a monitor.

System For Loading A Saved Write Pointer Into A Read Pointer Of A Storage At Desired Synchronization Points Within A Horizontal Video Line For Synchronizing Data

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US Patent:
6578093, Jun 10, 2003
Filed:
Jan 19, 2000
Appl. No.:
09/487138
Inventors:
Stephen F. Armen - Carlsbad CA
Benjamin Edwin Felta - Cardiff CA
Asif Shakeel - San Diego CA
Assignee:
Conexant Systems, Inc. - Newport Beach CA
International Classification:
G06F 506
US Classification:
710 52, 345547, 345558, 36518905
Abstract:
The frequency of use of video and other data is increasing. Additionally, video components are typically connected together. The video components may synchronize via a first in first out (“FIFO”) queue. Data may be written into the FIFO queue by a component with a first clock rate, and then the data may be read out of the FIFO queue by a component with a second clock rate. Because of the different clock rates, it is possible that there could be an underflow or overflow of data in the FIFO queue. Typically, when the timing between the components is far apart, the read and write pointers that point into the FIFO queue are realigned by using a reset control signal, which sets both pointers back to address zero of the FIFO queue. The present system provides an improved technique for synchronizing the read and write pointers. In particular, the present system provides a technique for aligning the read and write pointers of a FIFO queue at any time and at any random address.
Asif Shakeel from San Jose, CA, age ~53 Get Report